makefile 견본

makefile 견본

.SUFFIXES : .c .o

CC = gcc

INC =
LIBS =
CFLAGS = -g $(INC)

OBJS = tbl.o
SRCS = tbl.c

TARGET = table

all : $(TARGET)

$(TARGET) : $(OBJS)
    $(CC) -o $@ $(OBJS) $(LIBS)

dep :
    gccmakedep $(INC) $(SRCS)

clean :
    rm -rf $(OBJS) $(TARGET) core

new :
    $(MAKE) clean
    $(MAKE)

자주 쓰는데도 항상 까먹는  makefile!-_-/

PROGNAME = calctest
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c, %.o, $(SRCS))

CC = gcc
CFLAGS = -Wall
LDFLAGS =

$(PROGNAME): $(OBJS)
    $(CC) $(LDFLAGS) -o $PROGNAME $^

clean:
    rm -f $(PROGNAME) $(OBJS) depend

depend: $(SRCS)
    $(CC) $(CFLAGS) -MM $^ > $@

-include depend

참고 : http://www.viper.pe.kr/docs/make-ko/make-ko_8.html

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