makefile 견본
.SUFFIXES : .c .o
CC = gcc
INC =
LIBS =
CFLAGS = -g $(INC)
OBJS = tbl.o
SRCS = tbl.c
TARGET = table
all : $(TARGET)
$(TARGET) : $(OBJS)
$(CC) -o $@ $(OBJS) $(LIBS)
dep :
gccmakedep $(INC) $(SRCS)
clean :
rm -rf $(OBJS) $(TARGET) core
new :
$(MAKE) clean
$(MAKE)
자주 쓰는데도 항상 까먹는 makefile!-_-/
PROGNAME = calctest
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c, %.o, $(SRCS))
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c, %.o, $(SRCS))
CC = gcc
CFLAGS = -Wall
LDFLAGS =
$(PROGNAME): $(OBJS)
$(CC) $(LDFLAGS) -o $PROGNAME $^
clean:
rm -f $(PROGNAME) $(OBJS) depend
depend: $(SRCS)
$(CC) $(CFLAGS) -MM $^ > $@
-include depend